Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture
نویسندگان
چکیده
منابع مشابه
Reconfigurable scan architecture for test power and data volume reduction
With exponential development in the semiconductor technology in recent years, the magnitudes of test power consumption and test data volumes have increased significantly. This has resulted in over-testing because of IR drops. This paper proposes a reconfigurable scan architecture to overcome these challenges. The proposed architecture increases the flexibility of the scan partitioning technique...
متن کاملScan Cell Reordering for Peak Power Reduction during Scan Test Cycles
Scan technology increases the switching activity well beyond that of the functional operation of an IC. In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (i.e. between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we propose a s...
متن کاملScan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression r...
متن کاملTest Data Volume Reduction of Scan-Based Deterministic Test based on Scan Chains Compatibility using Partitioning & Relaxation
As IC design has entered into the nanometer scale integration, the design test complexity has increased tremendously because of the extent of sophistication possible at this integration level. Scan-based design test strategy is the most widely used solution to achieve the high level of fault coverage desired for such complex designs, and especially for the SoC based design paradigm. However, te...
متن کاملSelective scan slice repetition for simultaneous reduction of test power consumption and test data volume
In this paper, we present a selective scan slice encoding technique for power-aware test data compression. The proposed scheme dramatically reduces test data volume via scan slice repetition, and generates an adjacent-filled test pattern known as the favorable lowpower pattern mapping method. Experiments were performed on the large ITC’99 benchmark circuits, and results show the effectiveness o...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IPSJ Transactions on System LSI Design Methodology
سال: 2011
ISSN: 1882-6687
DOI: 10.2197/ipsjtsldm.4.140